Open-Source Hardware Projects
RISC-V Cores and SoC Overview - https://github.com/riscv/riscv-cores-list
Taxonomy of Open Source Processors - http://parallel.princeton.edu/openpiton/open_source_processors.php
- Ariane RISC-V CPU (SystemVerilog)
- BlackParrot (SystemVerilog)
- BOOM: The Berkeley Out-of-Order RISC-V Processor (Chisel)
- Davis In-Order (DINO) CPU models (Chisel)
- engine-V: SoftCPU/SoC engine-V (Verilog)
- f32c - A 32-bit RISC-V / MIPS retargetable CPU core (VHDL)
- FWRISC: a Featherweight RISC-V implementation of the RV32I instruction set
- HammerBlade RISC-V Manycore (SystemVerilog)
- HL5: A 32-bit RISC-V Processor Designed with High-Level Synthesis (SystemC)
- Ibex: a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a 2-stage pipeline (SystemVerilog)
- Icicle: 32-bit RISC-V system on chip for iCE40 and ECP5 FPGAs (SystemVerilog)
- lowRISC - creating a fully open-sourced, Linux-capable, RISC-V-based SoC (SystemVerilog)
- mriscv: A 32-bit Microcontroller featuring a RISC-V core (Verilog)
- ORCA - an implementation of RISC-V intended to target FPGAs (VHDL)
- PicoRV32 - A Size-Optimized RISC-V CPU (Verilog)
- PULPino - 32-bit RISC-V microcontroller core (SystemVerilog)
- PulseRain Reindeer: RISCV RV32I[M] Soft CPU (Verilog)
- RIDECORE (RIsc-v Dynamic Execution CORE) - Out-of-Order RISC-V processor (Verilog)
- RI5CY: RISC-V Core - PULP RI5CY core modified for Verilator modeling and as a GDB server (SystemVerilog)
- RISC-V VHDL: System-on-Chip (VHDL)
- riscv-simple-sv: A simple RISC V core for teaching (SystemVerilog)
- Riscy Processors - Open-Sourced RISC-V Processors (Bluespec System Verilog)
- Rocket Chip Generator (Chisel)
- RPU: Basic RISC-V CPU implementation in VHDL
- RSD: RISC-V Out-of-Order Superscalar Processor (SystemVerilog)
- https://github.com/rsd-devel/rsd
- An Open Source FPGA-Optimized Out-of-Order RISC-V Soft Processor
- IEEE International Conference on Field-Programmable Technology (FPT) 2019
- Susumu Mashimo, Akifumi Fujita, Reoma Matsuo, Seiya Akaki, Akifumi Fukuda, Toru Koizumi, Junichiro Kadomoto, Hidetsugu Irie, Masahiro Goshima, Koji Inoue, Ryota Shioya
- http://sv.rsg.ci.i.u-tokyo.ac.jp/pdfs/Mashimo-FPT'19.pdf
- SCR1: an open-source RISC-V compatible MCU core (SystemVerilog)
- SERV: The SErial RISC-V CPU (Verilog)
- SHAKTI Processor Project (Bluespec System Verilog; generated Verilog)
- SiFive's Freedom platforms RTL source files (Chisel)
- Sodor Processor Collection - educational microarchitectures (Chisel)
- SweRV RISC-V core from Western Digital (SystemVerilog)
- Taiga (SystemVerilog)
- 32-bit RISC-V processor designed for FPGAs supporting the Multiply/Divide and Atomic extensions (RV32IMA)
- https://gitlab.com/sfu-rcl/Taiga
- TAIGA: A new RISC-V soft-processor framework enabling high performance CPU architectural features
- VexRiscv: FPGA-friendly 32-bit RISC-V CPU implementation (SpinalHDL)
- YARVI - Yet Another RISC-V Implementation (Verilog)
Tools
https://riscv.org/software-tools/
Emulation & Simulation
- BRISC-V: an open-source, RISC-V based, full multicore, design space exploration platform
- Dromajo: Esperanto Technology's RISC-V Reference Model
- libriscv: RISC-V userspace emulator library
- MARSS-RISCV: Micro-Architectural System Simulator for RISC-V
- RARS: RISC-V Assembler and Runtime Simulator
- Ripes: A graphical 5-stage RISC-V pipeline simulator & assembly editor
- RISCVEmu Toy RISC-V emulator
- riscvOVPsim: A Complete, Fully Functional, Configurable RISC-V Simulator
- rv32-sail - high-level emulator for RV32IM
- rv8: RISC-V simulator for x86-64 - https://rv8.io/
- RVirt: RISC-V hypervisor written in Rust
- Spike, a RISC-V ISA Simulator
- TinyEMU
- https://bellard.org/tinyemu/
- TinyEMU is a system emulator for the RISC-V architecture. Its purpose is to be small and simple while being complete.
- venus: RISC-V instruction set simulator built for education
- WebRISC-V: a Web-Based Education-Oriented RISC-V Pipeline Simulation Environment
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Last modified 07 October 2024