RISC-V Software

Open-Source Hardware Projects

RISC-V Cores and SoC Overview - https://github.com/riscv/riscv-cores-list

Taxonomy of Open Source Processors - http://parallel.princeton.edu/openpiton/open_source_processors.php

Ariane RISC-V CPU (SystemVerilog)
- Ariane is a 6-stage, single issue, in-order CPU which implements the 64-bit RISC-V instruction set.
- https://pulp-platform.github.io/ariane/
- https://github.com/pulp-platform/ariane
BlackParrot (SystemVerilog)
- Linux-capable cache-coherent, RV64GC multicore
- https://github.com/black-parrot
- BlackParrot: An Agile Open Source RISC-V Multicore for Accelerator SoCs
  - FOSDEM 2020; Dan Petrisko
  - https://fosdem.org/2020/schedule/event/riscv_blackparrot/
BOOM: The Berkeley Out-of-Order RISC-V Processor (Chisel)
- https://ccelio.github.io/riscv-boom-doc/
- https://github.com/ucb-bar/riscv-boom
- https://twitter.com/boom_cpu
Davis In-Order (DINO) CPU models (Chisel)
- A teaching-focused RISC-V CPU design used at UC Davis
- https://github.com/jlpteaching/dinocpu
- The Davis In-Order (DINO) CPU: A Teaching-focused RISC-V CPU Design
  - Workshop on Computer Architecture Education (WCAE) 2019
  - Jason Lowe-Power and Christopher Nitta
  - Paper: https://arch.cs.ucdavis.edu/assets/papers/wcae19-dinocpu.pdf
  - Slides: https://arch.cs.ucdavis.edu/assets/papers/wcae19-dinocpu-presentation.pdf
engine-V: SoftCPU/SoC engine-V (Verilog)
- https://github.com/micro-FPGA/engine-V
f32c - A 32-bit RISC-V / MIPS retargetable CPU core (VHDL)
- https://github.com/f32c/f32c
FWRISC: a Featherweight RISC-V implementation of the RV32I instruction set
- https://github.com/mballance/fwrisc
- FWRISC: Sizing up the RISC-V Architecture
  - https://bitsbytesgates.blogspot.com/2018/12/fwrisc-sizing-up-risc-v-architecture.html
HammerBlade RISC-V Manycore (SystemVerilog)
- A programmable, scalable RISC-V fabric
- https://github.com/bespoke-silicon-group/bsg_bladerunner
- https://github.com/bespoke-silicon-group/bsg_manycore
- http://bjump.org/manycore/
- HammerBlade IR: https://capra.cs.cornell.edu/hbir/
- FOSDEM 2020; Michael Taylor
  - https://fosdem.org/2020/schedule/event/riscv_hammerblade/
HL5: A 32-bit RISC-V Processor Designed with High-Level Synthesis (SystemC)
- https://github.com/sld-columbia/hl5
- Custom Integrated Circuits Conference (CICC) 2020
  - Paolo Mantovani, Robert Margelli, Davide Giri, Luca P. Carloni
  - https://sld.cs.columbia.edu/pubs/mantovani_cicc20.pdf
Ibex: a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a 2-stage pipeline (SystemVerilog)
- https://github.com/lowRISC/ibex/
- https://www.lowrisc.org/blog/2019/06/an-update-on-ibex-our-microcontroller-class-cpu-core/
- How lowRISC made its Ibex RISC-V CPU core faster: Using open source tools to improve an open source core
  - FOSDEM 2020; Greg Chadwick
  - https://fosdem.org/2020/schedule/event/riscv_lowrisc/
Icicle: 32-bit RISC-V system on chip for iCE40 and ECP5 FPGAs (SystemVerilog)
- https://github.com/grahamedgecombe/icicle
lowRISC - creating a fully open-sourced, Linux-capable, RISC-V-based SoC (SystemVerilog)
- http://www.lowrisc.org/
- https://github.com/lowRISC/lowrisc-chip/
- https://twitter.com/lowRISC
mriscv: A 32-bit Microcontroller featuring a RISC-V core (Verilog)
- http://www.onchipuis.io/risc-v
- https://github.com/onchipuis/mriscv
- https://github.com/onchipuis/mriscvcore
- https://twitter.com/onchipUIS
ORCA - an implementation of RISC-V intended to target FPGAs (VHDL)
- https://github.com/VectorBlox/orca
PicoRV32 - A Size-Optimized RISC-V CPU (Verilog)
- https://github.com/cliffordwolf/picorv32
PULPino - 32-bit RISC-V microcontroller core (SystemVerilog)
- http://www.pulp-platform.org/
- https://github.com/pulp-platform/pulpino
- https://twitter.com/pulp_platform
PulseRain Reindeer: RISCV RV32I[M] Soft CPU (Verilog)
- https://github.com/PulseRain/Reindeer
RIDECORE (RIsc-v Dynamic Execution CORE) - Out-of-Order RISC-V processor (Verilog)
- https://github.com/ridecore/ridecore
RI5CY: RISC-V Core - PULP RI5CY core modified for Verilator modeling and as a GDB server (SystemVerilog)
- https://github.com/embecosm/ri5cy
- A dive into RI5CY core internals - https://www.embecosm.com/2019/08/13/a-dive-into-ri5cy-core-internals/
RISC-V VHDL: System-on-Chip (VHDL)
- VHDL implementation of the RISC-V System-on-Chip based on bare "Rocket Chip"
- http://sergeykhbr.github.io/riscv_vhdl/
- https://github.com/sergeykhbr/riscv_vhdl
riscv-simple-sv: A simple RISC V core for teaching (SystemVerilog)
- https://github.com/tilk/riscv-simple-sv
Riscy Processors - Open-Sourced RISC-V Processors (Bluespec System Verilog)
- https://github.com/csail-csg/riscy
Rocket Chip Generator (Chisel)
- https://github.com/ucb-bar/rocket-chip/
RPU: Basic RISC-V CPU implementation in VHDL
- https://github.com/Domipheus/RPU
- Designing a RISC-V CPU (TPU/RPU) in VHDL Series
  - http://labs.domipheus.com/blog/tpu-series-quick-links/
RSD: RISC-V Out-of-Order Superscalar Processor (SystemVerilog)
- https://github.com/rsd-devel/rsd
- An Open Source FPGA-Optimized Out-of-Order RISC-V Soft Processor
  - IEEE International Conference on Field-Programmable Technology (FPT) 2019
  - Susumu Mashimo, Akifumi Fujita, Reoma Matsuo, Seiya Akaki, Akifumi Fukuda, Toru Koizumi, Junichiro Kadomoto, Hidetsugu Irie, Masahiro Goshima, Koji Inoue, Ryota Shioya
  - http://sv.rsg.ci.i.u-tokyo.ac.jp/pdfs/Mashimo-FPT'19.pdf
SCR1: an open-source RISC-V compatible MCU core (SystemVerilog)
- https://github.com/syntacore/scr1
SERV: The SErial RISC-V CPU (Verilog)
- https://github.com/olofk/serv
SHAKTI Processor Project (Bluespec System Verilog; generated Verilog)
- http://rise.cse.iitm.ac.in/shakti.html
- SHAKTI Tutorial at the VLSI Design Conference - http://www.slideshare.net/GSMadhusudan/shaktivlsidtutorial
- https://bitbucket.org/casl/shakti_public
SiFive's Freedom platforms RTL source files (Chisel)
- https://github.com/sifive/freedom
Sodor Processor Collection - educational microarchitectures (Chisel)
- https://github.com/ucb-bar/riscv-sodor
SweRV RISC-V core from Western Digital (SystemVerilog)
- https://github.com/westerndigitalcorporation/swerv_eh1
Taiga (SystemVerilog)
- 32-bit RISC-V processor designed for FPGAs supporting the Multiply/Divide and Atomic extensions (RV32IMA)
- https://gitlab.com/sfu-rcl/Taiga
- TAIGA: A new RISC-V soft-processor framework enabling high performance CPU architectural features
  - Field Programmable Logic and Applications (FPL) 2017
  - E. Matthews and L. Shannon
  - https://doi.org/10.23919/FPL.2017.8056766
  - https://carrv.github.io/2017/papers/matthews-taiga-carrv2017.pdf
VexRiscv: FPGA-friendly 32-bit RISC-V CPU implementation (SpinalHDL)
- https://github.com/SpinalHDL/VexRiscv
YARVI - Yet Another RISC-V Implementation (Verilog)
- https://github.com/tommythorn/yarvi
- https://www.cl.cam.ac.uk/teaching/1516/ECAD+Arch/exercise-yarvi.html

Tools

https://riscv.org/software-tools/

Compiler Explorer with RISC-V support - https://cx.rv8.io/
Debian port - https://wiki.debian.org/RISC-V
hpm_counters: A simple utility for doing RISC-V Hardware Performance Monitor (HPM) perf monitoring - https://github.com/ccelio/riscv-hpmcounters
RISC-V Disassembler: Single file RISC-V Disassembler with support for RV32/RV64/RV128 IMAFDC
- https://github.com/michaeljclark/riscv-disassembler
RISC-V Meta – a suite of tools that operate on RISC-V ISA - https://github.com/michaeljclark/riscv-meta/
RISC-V support for LLVM projects - http://www.lowrisc.org/llvm/status/ - https://github.com/lowRISC/riscv-llvm
RISC-V Torture Test Generator - https://github.com/ucb-bar/riscv-torture
Xv6 for RISC-V
- https://github.com/mit-pdos/xv6-riscv
- a re-implementation of Dennis Ritchie's and Ken Thompson's Unix Version 6 (v6)
- loosely follows the structure and style of v6, but is implemented for a modern RISC-V multiprocessor using ANSI C
- xv6-riscv-book: Text describing xv6 on RISC-V
  - https://github.com/mit-pdos/xv6-riscv-book
  - 6.S081: Operating System Engineering - https://pdos.csail.mit.edu/6.828/

Emulation & Simulation

BRISC-V: an open-source, RISC-V based, full multicore, design space exploration platform
- https://ascslab.org/research/briscv/index.html
- BRISC-V Explorer (RTL) - http://ascslab.org/research/briscv/explorer/explorer.html
- BRISC-V Simulator (Assembly) - http://ascslab.org/research/briscv/simulator/simulator.html
- The BRISC-V Platform: A Practical Teaching Approach for Computer Architecture
  - Workshop on Computer Architecture Education (WCAE) 2019
  - Rashmi Agarwal, Sahan Bandara, Alan Ehret, Mihailo Isakov, Miguel Mark, Michel A. Kinsy
  - Paper: https://ascslab.org/research/briscv/wcae/a1-agrawal.pdf
  - Slides: https://drive.google.com/file/d/1j969LvF8yN8OBsq58schBLjSh6Lfjbba/view
Dromajo: Esperanto Technology's RISC-V Reference Model
- RISC-V RV64GC emulator designed for RTL co-simulation
- https://github.com/chipsalliance/dromajo
libriscv: RISC-V userspace emulator library
- https://github.com/fwsGonzo/libriscv
- C++17 RISC-V RV32GC userspace emulator library
MARSS-RISCV: Micro-Architectural System Simulator for RISC-V
- https://github.com/bucaps/marss-riscv
RARS: RISC-V Assembler and Runtime Simulator
- https://github.com/TheThirdOne/rars
Ripes: A graphical 5-stage RISC-V pipeline simulator & assembly editor
- https://github.com/mortbopet/Ripes
RISCVEmu Toy RISC-V emulator
- https://github.com/jdryg/RISCVEmu
riscvOVPsim: A Complete, Fully Functional, Configurable RISC-V Simulator
- https://github.com/riscv/riscv-ovpsim
rv32-sail - high-level emulator for RV32IM
- https://github.com/thoughtpolice/rv32-sail
- https://riscv.ls0f.pw/
rv8: RISC-V simulator for x86-64 - https://rv8.io/
- https://github.com/rv8-io/rv8
RVirt: RISC-V hypervisor written in Rust
- https://github.com/mit-pdos/RVirt
- an S-mode trap-and-emulate hypervisor for RISC-V
Spike, a RISC-V ISA Simulator
- https://github.com/riscv/riscv-isa-sim
TinyEMU
- https://bellard.org/tinyemu/
- TinyEMU is a system emulator for the RISC-V architecture. Its purpose is to be small and simple while being complete.
venus: RISC-V instruction set simulator built for education
- https://venus.cs61c.org/
- https://github.com/ThaumicMekanism/venus
WebRISC-V: a Web-Based Education-Oriented RISC-V Pipeline Simulation Environment
- http://www.dii.unisi.it/~giorgi/WebRISC-V
- source code: http://www.dii.unisi.it/~giorgi/WebRISC-V/download
- Workshop on Computer Architecture Education (WCAE) 2019
- Roberto Giorgi and Gianfranco Mariotti
- Paper: http://www.dii.unisi.it/~giorgi/papers/Giorgi19-wcae.pdf
- Slides: http://www.dii.unisi.it/~giorgi/giorgi19-wcae_slides.pdf

Tags: language assembly native tool library

Last modified 16 December 2024

RISC-V Software

A collection of links to software (tools, libraries, etc) around the RISC-V CPU/assembly specification.

Open-Source Hardware Projects

Tools

Emulation & Simulation